Nonvolatile memory retains stored data when power is removed, which is required or at least highly desirable in many different types of computers and other electronic devices. Improvements in the various processes used for fabricating the various types of nonvolatile memory tend to lag improvements in widely used processes such as the advanced CMOS logic process. For example, processes for devices such as flash EEPROM devices tend to use 30% more mask steps than the standard advanced CMOS logic process to produce the various special regions and structures required for the high voltage generation circuits, the triple well, the floating gate, the ONO layers, and the special source and drain junctions typically found in such devices.
Accordingly, processes for flash devices tend to be one or two generations behind the standard advanced CMOS logic process and about 30% more expensive on a cost-per-wafer basis. As another example, processes for antifuses must be suitable for fabricating various antifuse structures and high voltage circuits, and so also tend to be about one generation behind the standard advanced CMOS process.
In our co-pending U.S. Patent Application U.S. patent application Ser. No. 10/024,327 filed on Dec. 17, 2001 and U.S. patent application Ser. No. 09/955,641 filed Sep. 18, 2001, there is described a CMOS process compatible single-poly nonvolatile memory cell and array. The disclosed nonvolatile memory cell has the advantage of low cost and high reliability. Because of the novel nature of the nonvolatile memory described in our co-pending applications, conventional testing tools used for flash memory are not suitable. Therefore, the present invention provides circuits and methods for testing of nonvolatile memory using gate oxide breakdown.